CMOS

Complementary metal–oxide–semiconductor (CMOS) (play /ˈsiːmɒs/) is a technology for amalgam dent circuits. CMOS technology is acclimated in microprocessors, microcontrollers, changeless RAM, and added agenda argumentation circuits. CMOS technology is aswell acclimated for several analog circuits such as angel sensors (CMOS sensor), abstracts converters, and awful dent transceivers for abounding types of communication. Frank Wanlass patented CMOS in 1967 (US apparent 3,356,858).

CMOS is aswell sometimes referred to as complementary-symmetry metal–oxide–semiconductor (or COS-MOS).1 The words "complementary-symmetry" accredit to the actuality that the archetypal agenda architecture appearance with CMOS uses commutual and balanced pairs of p-type and n-type metal oxide semiconductor acreage aftereffect transistors (MOSFETs) for argumentation functions.

Two important characteristics of CMOS accessories are top babble amnesty and low changeless ability consumption. Significant ability is alone fatigued if the transistors in the CMOS accessory are switching amid on and off states. Consequently, CMOS accessories do not aftermath as abundant decay calefaction as added forms of logic, for archetype transistor-transistor argumentation (TTL) or NMOS logic. CMOS aswell allows a top body of argumentation functions on a chip. It was primarily for this acumen that CMOS became the a lot of acclimated technology to be implemented in VLSI chips.

The byword "metal–oxide–semiconductor" is a advertence to the concrete anatomy of assertive field-effect transistors, accepting a metal aboideau electrode placed on top of an oxide insulator, which in about-face is on top of a semiconductor material. Aluminium was already acclimated but now the actual is polysilicon. Added metal gates accept fabricated a improvement with the appearance of high-k dielectric abstracts in the CMOS process, as appear by IBM and Intel for the 45 nanometre bulge and beyond.2

Technical details

"CMOS" refers to both a accurate appearance of agenda chip design, and the ancestors of processes acclimated to apparatus that chip on chip circuits (chips). CMOS chip dissipates beneath ability than argumentation families with arresting loads. Back this advantage has added and developed added important, CMOS processes and variants accept appear to dominate, appropriately the all-inclusive majority of avant-garde chip ambit accomplishment is on CMOS processes.3 As of 2010, CPUs with the best achievement per watt anniversary year accept been CMOS changeless argumentation back 1976.citation needed

CMOS circuits use a aggregate of p-type and n-type metal–oxide–semiconductor field-effect transistors (MOSFETs) to apparatus argumentation gates and added agenda circuits begin in computers, telecommunications equipment, and arresting processing equipment. Although CMOS argumentation can be implemented with detached accessories (e.g., for advisory purposes in an anterior circuits class), archetypal bartering CMOS articles are chip circuits composed of millions of transistors of both types on a ellipsoidal section of silicon of amid 10 and 400mm2.citation needed These accessories are frequently alleged "chips", although aural the industry they are aswell referred to as a "die" (singular), "dice" (plural), or "dies" (plural).

Composition

The capital assumption abaft CMOS circuits that allows them to apparatus argumentation gates is the use of p-type and n-type metal–oxide–semiconductor field-effect transistors to actualize paths to the achievement from either the voltage antecedent or ground. If a aisle to achievement is created from the voltage source, the ambit is said to be pulled up. The added ambit accompaniment occurs if a aisle to achievement is created from arena and the achievement pulled down to the arena potential.

Inversion

CMOS circuits are complete in such a way that all PMOS transistors accept to accept either an ascribe from the voltage antecedent or from addition PMOS transistor. Similarly, all NMOS transistors accept to accept either an ascribe from arena or from addition NMOS transistor. The agreement of a PMOS transistor creates low attrition amid its antecedent and cesspool contacts if a low aboideau voltage is activated and top attrition if a top aboideau voltage is applied. On the added hand, the agreement of an NMOS transistor creates top attrition amid antecedent and cesspool if a low aboideau voltage is activated and low attrition if a top aboideau voltage is applied. CMOS accomplishes accepted abridgement by complementing every nMOSFET with a pMOSFET and abutting both gates and both drains together. A top voltage on the gates will could cause the nMOSFET to conduct and the pMOSFET not to conduct while a low voltage on the gates causes the reverse. This adjustment abundantly reduces ability burning and calefaction generation. However, during the switching time both MOSFETs conduct briefly as the aboideau voltage goes from one accompaniment to another. This induces a abrupt fasten in ability burning and becomes a austere affair at top frequencies.

The angel on the appropriate shows what happens if an ascribe is affiliated to both a PMOS transistor (top of diagram) and an NMOS transistor (bottom of diagram). If the voltage of ascribe A is low, the NMOS transistor's approach is in a top attrition state. This banned the accepted that can breeze from Q to ground. The PMOS transistor's approach is in a low attrition accompaniment and abundant added accepted can breeze from the accumulation to the output. Because the attrition amid the accumulation voltage and Q is low, the voltage bead amid the accumulation voltage and Q due to a accepted fatigued from Q is small. The achievement accordingly registers a top voltage.

On the added hand, if the voltage of ascribe A is high, the PMOS transistor is in an OFF (high resistance) accompaniment so it would absolute the accepted abounding from the absolute accumulation to the output, while the NMOS transistor is in an ON (low resistance) state, acceptance the achievement to cesspool to ground. Because the attrition amid Q and arena is low, the voltage bead due to a accepted fatigued into Q agreement Q aloft arena is small. This low bead after-effects in the achievement registering a low voltage.

In short, the outputs of the PMOS and NMOS transistors are commutual such that if the ascribe is low, the achievement is high, and if the ascribe is high, the achievement is low. Because of this behaviour of ascribe and output, the CMOS circuits' achievement is the changed of the input.

A agenda on nomenclature: 4 The ability food for CMOS are alleged VDD and VSS, or VCC and Ground(GND) depending on the manufacturer. VDD and VSS are carryovers from accepted MOS circuits and angle for the cesspool and antecedent supplies. These do not administer anon to CMOS back both food are absolutely antecedent supplies. VCC and Arena are carryovers from TTL argumentation and that classification has been retained with the addition of the 54C/74C band of CMOS.

Duality

An important appropriate of a CMOS ambit is the duality that exists amid its PMOS transistors and NMOS transistors. A CMOS ambit is created to acquiesce a aisle consistently to abide from the achievement to either the ability antecedent or ground. To achieve this, the set of all paths to the voltage antecedent accept to be the accompaniment of the set of all paths to ground. This can be calmly able by defining one in agreement of the NOT of the other. Due to the De Morgan's laws based logic, the PMOS transistors in alongside accept agnate NMOS transistors in alternation while the PMOS transistors in alternation accept agnate NMOS transistors in parallel.

Logic

More circuitous argumentation functions such as those involving AND and OR gates crave manipulating the paths amid gates to represent the logic. If a aisle consists of two transistors in series, both transistors accept to accept low attrition to the agnate accumulation voltage, modelling an AND. If a aisle consists of two transistors in parallel, either one or both of the transistors accept to accept low attrition to affix the accumulation voltage to the output, modelling an OR.

Shown on the appropriate is a ambit diagram of a NAND aboideau in CMOS logic. If both of the A and B inputs are high, again both the NMOS transistors (bottom bisected of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive aisle will be accustomed amid the achievement and Vss (ground), bringing the achievement low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive aisle will be accustomed amid the achievement and Vdd (voltage source), bringing the achievement high.

An advantage of CMOS over NMOS is that both low-to-high and high-to-low achievement transitions are fast back the pull-up transistors accept low attrition if switched on, clashing the amount resistors in NMOS logic. In addition, the achievement arresting swings the abounding voltage amid the low and top rails. This strong, added about symmetric acknowledgment aswell makes CMOS added aggressive to noise.

See Logical accomplishment for a adjustment of artful adjournment in a CMOS circuit.

Power: switching and leakage

CMOS argumentation dissipates beneath ability than NMOS argumentation circuits because CMOS dissipates ability alone if switching ("dynamic power"). On a archetypal ASIC in a avant-garde 90 nanometer process, switching the achievement ability yield 120 picoseconds, and appear already every ten nanoseconds. NMOS argumentation dissipates ability whenever the transistor is on, because there is a accepted aisle from Vdd to Vss through the amount resistor and the n-type network.

Static CMOS gates are actual ability able because they blow about aught ability if idle. Earlier, the ability burning of CMOS accessories was not the above affair while designing chips. Factors like acceleration and breadth bedeviled the architecture parameters. As the CMOS technology confused beneath sub-micron levels the ability burning per assemblage breadth of the dent has risen tremendously.

Broadly classifying, ability amusement in CMOS circuits occurs because of two components:

Static dissipation

Sub beginning action if the transistors are off.

Both NMOS and PMOS transistors accept a gate–source beginning voltage, beneath which the accepted (called sub beginning current) through the accessory drops exponentially. Historically, CMOS designs operated at accumulation voltages abundant beyond than their beginning voltages (Vdd ability accept been 5 V, and Vth for both NMOS and PMOS ability accept been 700 mV). A appropriate blazon of the CMOS transistor with abreast aught beginning voltage is the built-in transistor.

Tunnelling accepted through aboideau oxide.

SiO2 is a actual acceptable insulator, but at actual baby array levels electrons can adit beyond the actual attenuate insulation; the anticipation drops off exponentially with oxide thickness. Tunnelling accepted becomes actual important for transistors beneath 130 nm technology with aboideau oxides of 20 Å or thinner.

Arising accepted through about-face biased diodes.

Baby about-face arising currents are formed due to accumulation of about-face bent amid circulation regions and wells (for e.g., p-type circulation vs. n-well), wells and substrate (for e.g., n-well vs. p-substrate). In avant-garde action diode arising is actual baby compared to sub beginning and tunnelling currents, so these may be alone during ability calculations.

Contention accepted in ratioed circuit

Activating Dissipation

Charging and absolution of amount capacitances.

CMOS circuits blow ability by charging the assorted amount capacitances (mostly aboideau and wire capacitance, but aswell cesspool and some antecedent capacitances) whenever they are switched. In one complete aeon of CMOS logic, accepted flows from VDD to the amount capacitance to allegation it and afresh flows from the answerable amount capacitance to arena during discharge. Therefore in one complete charge/discharge cycle, a absolute of Q=CLVDD is appropriately transferred from VDD to ground. Accumulate by the switching abundance on the amount capacitances to get the accepted used, and accumulate by voltage afresh to get the appropriate switching ability blown by a CMOS device: P = C V^2 f .

Back a lot of gates do not operate/switch at every alarm cycle, they are generally accompanied by a agency \alpha, alleged the action factor. Now, the activating ability amusement may be re-written as P = \alpha C V^2 f .

A alarm in a arrangement has an action agency α=1, back it rises and avalanche every cycle. A lot of abstracts has an action agency of 0.5. If actual amount capacitance is estimated on a bulge calm with its action factor, the activating ability amusement at that bulge can be affected effectively.

Abbreviate ambit ability dissipation

Back there is a bound rise/fall time for both pMOS and nMOS, during transition, for example, from off to on, both the transistors will be on for a baby aeon of time in which accepted will acquisition a aisle anon from VDD to ground, appropriately creating a abbreviate ambit current. Abbreviate ambit ability amusement increases with acceleration and abatement time of the transistors.

An added anatomy of ability burning became cogent in the 1990s as affairs on dent became narrower and the continued affairs became added resistive. CMOS gates at the end of those arresting affairs see apathetic ascribe transitions. During the average of these transitions, both the NMOS and PMOS argumentation networks are partially conductive, and accepted flows anon from Vdd to VSS. The ability appropriately acclimated is alleged crowbar power. Careful architecture which avoids abominably apprenticed continued angular affairs has ameliorated this effect, and crowbar ability is about consistently essentially abate than switching power.

To acceleration up designs, manufacturers accept switched to constructions that accept lower voltage thresholds but because of this a avant-garde NMOS transistor with a Vth of 200 mV has a cogent subthreshold arising current. Designs (e.g. desktop processors) which cover all-inclusive numbers of circuits which are not actively switching still absorb ability because of this arising current. Arising ability is a cogent allocation of the absolute ability captivated by such designs. Multi-threshold CMOS (MTCMOS), now accessible from foundries, is one access to managing arising power. With MTCMOS, top Vth transistors are acclimated if switching acceleration is not critical, while low Vth transistors are acclimated in acceleration acute paths. Further technology advances that use even thinner aboideau dielectrics accept an added arising basic because of accepted tunnelling through the acutely attenuate aboideau dielectric. Application high-k dielectrics instead of silicon dioxide that is the accepted aboideau dielectric allows agnate accessory performance, but with a thicker aboideau insulator, appropriately alienated this current. Arising ability abridgement application new actual and arrangement designs is analytical to comestible ascent of CMOS.5

Analog CMOS

Besides agenda applications, CMOS technology is aswell acclimated in analog applications. For example, there are CMOS operational amplifier ICs accessible in the market. Transmission gates may be acclimated instead of arresting relays. CMOS technology is aswell broadly acclimated for RF circuits all the way to bake frequencies, in mixed-signal (analog+digital) applications.

Temperature range

Conventional CMOS accessories plan over a ambit of −55 °C to +125 °C. There were abstract break as aboriginal as August 2008 that silicon CMOS will plan down to −233 °C (40 K).6 Functioning temperatures abreast 40 K accept back been accomplished application overclocked AMD Phenom II processors with a aggregate of aqueous nitrogen and aqueous helium cooling.7