More circuitous argumentation functions such as those involving AND and OR gates crave manipulating the paths amid gates to represent the logic. If a aisle consists of two transistors in series, both transistors accept to accept low attrition to the agnate accumulation voltage, modelling an AND. If a aisle consists of two transistors in parallel, either one or both of the transistors accept to accept low attrition to affix the accumulation voltage to the output, modelling an OR.
Shown on the appropriate is a ambit diagram of a NAND aboideau in CMOS logic. If both of the A and B inputs are high, again both the NMOS transistors (bottom bisected of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive aisle will be accustomed amid the achievement and Vss (ground), bringing the achievement low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive aisle will be accustomed amid the achievement and Vdd (voltage source), bringing the achievement high.
An advantage of CMOS over NMOS is that both low-to-high and high-to-low achievement transitions are fast back the pull-up transistors accept low attrition if switched on, clashing the amount resistors in NMOS logic. In addition, the achievement arresting swings the abounding voltage amid the low and top rails. This strong, added about symmetric acknowledgment aswell makes CMOS added aggressive to noise.
See Logical accomplishment for a adjustment of artful adjournment in a CMOS circuit.
Shown on the appropriate is a ambit diagram of a NAND aboideau in CMOS logic. If both of the A and B inputs are high, again both the NMOS transistors (bottom bisected of the diagram) will conduct, neither of the PMOS transistors (top half) will conduct, and a conductive aisle will be accustomed amid the achievement and Vss (ground), bringing the achievement low. If either of the A or B inputs is low, one of the NMOS transistors will not conduct, one of the PMOS transistors will, and a conductive aisle will be accustomed amid the achievement and Vdd (voltage source), bringing the achievement high.
An advantage of CMOS over NMOS is that both low-to-high and high-to-low achievement transitions are fast back the pull-up transistors accept low attrition if switched on, clashing the amount resistors in NMOS logic. In addition, the achievement arresting swings the abounding voltage amid the low and top rails. This strong, added about symmetric acknowledgment aswell makes CMOS added aggressive to noise.
See Logical accomplishment for a adjustment of artful adjournment in a CMOS circuit.
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